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STD50N03L STD50N03L-1
N-CHANNEL 30V - 9.2m - 40A - DPAK/IPAK STripFETTM III Power MOSFET
General features
Type STD50N03L STD50N03L-1

VDSS 30V 30V
RDS(on) 10.5m 10.5m
ID 40A 40A
3 2 1
3 1
RDS(on)*Qg industry's benchmark Conduction losses reduced Switching losses reduced Low threshold device
IPAK
DPAK
Description
This product utilizes the latest advanced design rules of ST's proprietary STripFETTM technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved.
Internal schematic diagram
Applications
Switching applications
Order codes
Part number STD50N03L STD50N03L-1 Marking D50N03L D50N03L Package DPAK IPAK Packaging Tape & reel Tube
October 2006
Rev 2
1/16
www.st.com 16
Contents
STD50N03L - STD50N03L-1
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
3 4 5 6
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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STD50N03L - STD50N03L-1
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS ID
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC=100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor Value 30 20 40 36 160 60 0.4 230 -55 to 175 Unit V V A A A W W/C mJ C
ID IDM
(2)
PTOT EAS(3) TJ Tstg
Single pulse avalanche energy Operating junction temperature Storage temperature
1. Limited by wire bonding 2. Pulse width limited by safe operating area 3. Starting Tj = 25C, ID =20A, VDD =15V
Table 2.
Symbol RthJ-Case RthJ-Amb Tj
Thermal data
Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose Value 2.5 100 275 Unit C/W C/W C
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Electrical characteristics
STD50N03L - STD50N03L-1
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250A, VGS= 0 VDS = 30V VDS = 30V, Tc=125C VGS = 20V VDS= VGS, ID = 250A VGS= 10V, ID= 20A VGS= 5V, ID= 20A 1 9.2 0.012 10.5 0.019 Min. 30 1 10
100
Typ.
Max.
Unit V A A nA V m
Table 4.
Symbol Ciss Coss Crss Qg Qgs Qgd QOSS (1)
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Output charge Test conditions VDS =25V, f=1MHz, VGS=0 VDD= 15V, ID = 40A VGS = 5V (see Figure 13) VDS = 24V ; VGS =0 f=1MHz Gate Bias Bias=0 Test signal Level=20mV open drain Min. Typ. 1434 294 48 10.4 5.1 3.7 12.6 14 Max. Unit pF pF pF nC nC nC nC
RG
Gate input resistance
1.1
1. QOSS=COSS*D Vin; COSS= Cgd + Cgd. See Appendix A
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STD50N03L - STD50N03L-1
Electrical characteristics
Table 5.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Test conditions VDD=15V, ID= 25A, RG= 4.7, VGS= 4.5V (see Figure 12) VDD= 15V, ID= 25A, RG= 4.7, VGS= 4.5V (see Figure 12) Min. Typ. 15 125 Max. Unit ns ns
Turn-off delay time Fall time
14 45
ns ns
Table 6.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 20A, VGS=0 ISD= 40A, di/dt = 100A/s, VDD= 10 V, Tj = 25C (see Figure 17) ISD= 40A, di/dt = 100A/s, VDD= 10V, Tj= 150C (see Figure 17) 26 15.6 1.2 26.4 18.1 1.4 Test conditions Min. Typ. Max. 40 160 1.3 Unit A A V ns nC A ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
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Electrical characteristics
STD50N03L - STD50N03L-1
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
Figure 5.
Normalized BVDSS vs temperature
Figure 6.
Static drain-source on resistance
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STD50N03L - STD50N03L-1 Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
7/16
Test circuit
STD50N03L - STD50N03L-1
3
Test circuit
Figure 13. Gate charge test circuit
Figure 12. Switching times test circuit for resistive load
Figure 14. Test circuit for inductive load Figure 15. Unclamped Inductive load test switching and diode recovery times circuit
Figure 16. Unclamped inductive waveform
Figure 17. Switching time waveform
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STD50N03L - STD50N03L-1
Buck converter
Appendix A
Buck converter
Figure 18. Power losses estimation
The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires:

Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate Small Qg to have a faster commutation and to reduce gate charge losses
The high side (SW1) device requires:

Low RDS(on) to reduce the conduction losses.
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Buck converter Table 7. Power losses
High side switching (SW1)
STD50N03L - STD50N03L-1
Low side switch (SW2)
Pconduction
R DS(on)SW1 * I 2 * L
R DS(on)SW2 * I 2 * (1 - ) L
IL Ig
Pswitching
Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *
Zero Voltage Switching
Recovery
(1)
Not applicable
Vin * Q rr(SW2) * f
Pdiode Conduction Not applicable
Vf(SW2) * I L * t deadtime * f Q gls(SW2) * Vgg * f
Vin * Q oss(SW2) * f 2
Pgate(QG)
Q g(SW1) * Vgg * f
PQoss
Vin * Q oss(SW1) * f 2
1. Dissipated by SW1 during turn-on
Table 8.
Paramiters meaning
Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses
Parameter d Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss
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STD50N03L - STD50N03L-1
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com
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Package mechanical data
STD50N03L - STD50N03L-1
TO-251 (IPAK) MECHANICAL DATA
DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033
H C A C2 L2 D B3 B6 A1 L
= =
3
B5
B
A3
=
B2
=
G
=
E
L1
1
2
=
0068771-E
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STD50N03L - STD50N03L-1
Package mechanical data
DPAK MECHANICAL DATA
mm. DIM. MIN. A A1 A2 B b4 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 5.1 6.4 4.7 2.28 4.4 9.35 1 2.8 0.8 0.6 0.2 0 8 0 1 0.023 0.008 8 4.6 10.1 0.173 0.368 0.039 0.110 0.031 0.039 6.6 0.252 0.185 0.090 0.181 0.397 TYP MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.200 0.260 TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 inch
0068772-F
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Packaging mechanical data
STD50N03L - STD50N03L-1
5
Packaging mechanical data
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK QTY 2500 inch MIN. MAX. 12.992
TAPE MECHANICAL DATA
DIM. A0 B0 B1 D D1 E F K0 P0 P1 P2 R
W
BASE QTY 2500
mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40
15.7 16.3
inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574
0.618 0.641
MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1
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STD50N03L - STD50N03L-1
Revision history
6
Revision history
Table 9.
Date 31-Jul-2006 27-Oct-2006
Revision history
Revision 1 2 Initial release. Modified Figure 1.: Safe operating area on page 6 Changes
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STD50N03L - STD50N03L-1
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